Please forward this error screen to 173. The PCI specification defines two types of connectors that may be implemented at maximum pci slots motherboard system board level: One for systems that implement 5 Volt signaling levels, and one for systems that implement 3. In addition, PCI systems may implement either the 32-bit or 64-bit connector. Most PCI buses implement only the 32-bit portion of the connector which consists of pins 1 through 62.
Advanced systems which support 64-bit data transfers implement the full PCI bus connector which consists of pins 1 through 94. Three types of add-in boards may be implemented: 5 Volt add-in boards include a key notch in pin positions 50 and 51 to allow them to be plugged only into 5 Volt system connectors.
3 Volt add-in boards include a key notch in pin positions 12 and 13 to allow them to be plugged only into 3. Universal add-in boards include both key notches to allow them to be plugged into either 5 Volt or 3.
Notes: Pin 63-94 exists only on 64 bit PCI implementations. 3V boards, 5V on 5V boards, and define signal rails on the Universal board.
The initial PCI specification permitted a maximum clock rate of 33 MHz allowing one bus transfer to be performed every 30 nanoseconds. 1 of the PCI specification extended the bus definition to support operation at 66 MHz, but the vast majority of todays personal computers continue to implement a PCI bus that runs at a maximum speed of 33 MHz. It architects a means of supporting a 64-bit data bus through a longer connector slot, but most of todays personal computers support only 32-bit data transfers through the base 32-bit PCI connector. The multiplexed Address and Data bus allows a reduced pin count on the PCI connector that enables lower cost and smaller package size for PCI components.
Typical 32-bit PCI add-in boards use only about 50 signals pins on the PCI connector of which 32 are the multiplexed Address and Data bus. PCI bus cycles are initiated by driving an address onto the AD signals during the first clock edge called the address phase.
The next clock edge begins the first of one or more data phases in which data is transferred over the AD signals. In PCI terminology, data is transferred between an initiator which is the bus master, and a target which is the bus slave. A PCI bus transfer consists of one address phase and any number of data phases.
O operations that access registers within PCI targets typically have only a single data phase. Memory transfers that move blocks of data consist of multiple data phases that read or write multiple consecutive memory locations. Both the initiator and target may terminate a bus transfer sequence at any time. Arbitration in PCI is hidden in the sense that it does not consume clock cycles.
The current initiators bus transfers are overlapped with the arbitration process that determines the next owner of the bus. PCI supports a rigorous auto configuration mechanism.